Recently, a multi-domain vertical aligned (MVA) mode LCD has been developed as a liquid crystal display device with improved viewing angle characteristic and used in LCD TV sets, among other things. A VA mode LCD conducts a display operation in normally black mode by using, in combination, a vertical alignment liquid crystal layer, in which liquid crystal molecules are aligned perpendicularly to the substrate surface when no voltage is applied thereto, and two polarizers that are arranged as crossed Nicols with the liquid crystal layer interposed between them.
As disclosed in Patent Document No. 1, an MVA mode LCD defines the falling directions of liquid crystal molecules upon the application of a voltage by providing linear domain regulating means on both sides of the liquid crystal layer, thereby defining multiple domains in which the liquid crystal molecules have mutually different alignment directions (also called “directors”) in a single pixel (which is a so-called “multi-domain structure”). Such a structure in which multiple domains with mutually different alignment directions are defined in a single pixel is sometimes called an “alignment division structure”. Among various multi-domain structures, a four-domain structure is most popular. In that case, the four alignment directions are arranged so as to evenly split the angle defined by the respective axes of polarization of the two polarizers that are arranged as crossed Nicols. By adopting such a multi-domain structure, a wide viewing angle is realized.
A technique for reducing the viewing angle dependence of the γ characteristic of an MVA mode LCD is disclosed in Patent Document No. 2. The “γ characteristic” refers to the grayscale dependence of a display luminance. That is to say, if the γ characteristic has viewing angle dependence, it means that the display luminance will vary depending on whether an image with a certain grayscale is viewed straight or obliquely. Such a variation in display luminance corresponding to grayscale according to the viewing direction would be a problem particularly when a still picture such as a photo or a TV broadcast is presented on the LCD.
According to the technique disclosed in Patent Document No. 2, each pixel has at least first and second subpixels that can exhibit mutually different luminances at a certain grayscale. Thus, such a technique is called a “pixel division (or multi-pixel) technique” and such an LCD is termed an LCD with a “pixel division (or multi-pixel) structure”.
Hereinafter, an MVA mode LCD with a conventional multi-pixel structure will be described with reference to FIG. 41, which schematically illustrates the structure of two pixels that are adjacent to each other in the column direction in a huge number of pixels that are arranged in columns and rows to define a matrix pattern. The basic configuration of the present invention is identical with this structure. And the following statement will apply to the liquid crystal display device of the present invention, too.
Each pixel P of this liquid crystal display device 900 has two subpixels (which will be referred to herein as a “first subpixel SP-1” and a “second subpixel SP-2”, respectively). The LCD 900 further includes: a plurality of source bus lines (S bus lines), each of which is associated with a particular column of pixels; a plurality of gate bus lines (G bus lines), each of which is associated with a particular row of pixels; a plurality of TFTs, each of which is associated with one of the first and second subpixels SP-1 and SP-2 in an associated one of the pixels; and a plurality of CS bus lines, each of which is associated with either the respective first subpixels SP-1 or the respective second subpixels SP-2 on a particular row of pixels.
For example, an S bus line (i) is associated with an ith column of pixels, a G bus line (j) is associated with a jth row of pixels, TFT-1 is associated with the first subpixel SP-1 and TFT-2 is associated with the second subpixel SP-2. The respective gate electrodes of TFT-1 and TFT-2 are both connected to the same G bus line in common and have their ON and OFF states controlled with the same gate signal voltage applied. The respective source electrodes of TFT-1 and TFT-2 are both connected to the same S bus line in common. And when TFT-1 and TFT-2 are turned ON, a source signal voltage is written through the same S bus line on the first and second subpixels SP-1 and SP-2. The multiple pixels that form the display area of the liquid crystal display device are scanned with the gate signal voltage supplied to each of those G bus lines.
Each of the first and second subpixels SP-1 and SP-2 that each pixel P has includes a liquid crystal capacitor and a storage capacitor. The liquid crystal capacitor is formed by a subpixel electrode, the liquid crystal layer, and a counter electrode that faces the subpixel electrode through the liquid crystal layer. The storage capacitor is formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer (such as a gate insulating film), and a storage capacitor counter electrode that faces the storage capacitor electrode with the insulating layer interposed between them. Optionally, the storage capacitor electrode could the subpixel electrode itself. Also, the storage capacitor counter electrode could form part of a CS bus line (which will also be referred to herein as a “storage capacitor line”). In FIG. 41, each subpixel electrode is connected to the drain electrode of its associated TFT and is arranged so as to partially overlap with its associated CS bus line, thereby forming each storage capacitor.
For instance, the first subpixels SP-1 of the jth row of pixels are associated with a CS bus line CS-A and the second subpixels SP-2 of the jth row of pixels are associated with a CS bus line CS-B. These CS bus lines CS-A and CS-B are electrically independent of each other. That is why by controlling the CS voltages (which will also be referred to herein as “storage capacitor voltages”) supplied through the CS bus lines CS-A and CS-B, the first and second subpixels SP-1 and SP-2 can exhibit mutually different luminances as will be described later.
As an example, a situation where a write pulse (which will be referred to herein as “gate ON pulse Pw”) is applied to the G bus line (j) and a positive source signal voltage is written on a pixel at the intersection between the jth row and ith column will be described. It should be noted that in this description, the polarity of each of various kinds of voltages is defined with, respect to the counter voltage unless stated otherwise. Nevertheless, the reference voltage to determine the polarity does not have to perfectly agree with the counter voltage in a strict sense. On the other hand, the polarity of a CS voltage is determined with respect to the center value of the CS voltage. Furthermore, the “inversion of the polarity” of a CS voltage refers to not only a simple inversion of the polarity of the CS voltage into a positive or negative one but also a change of a CS voltage level toward the positive or negative side as well. The center value of a CS voltage typically agrees with, but does not always have to agree with, the counter voltage.
With TFT-1 and TFT-2 turned ON, a positive source signal voltage is written on the pixel at the intersection between the jth row and the ith column. After that, the CS voltage applied through the CS bus line CS-A to the storage capacitor of the first subpixel SP-1 is controlled such that its first change of voltage levels after TFT-1 has been turned OFF is a voltage increase. On the other hand, the CS voltage applied through the CS bus line CS-B to the storage capacitor of the second subpixel SP-2 is controlled such that its first change of voltage levels after TFT-2 has been turned OFF is a voltage decrease. That is to say, CS voltages with such waveforms are supplied through the CS bus lines CS-A and CS-B. With a positive source signal voltage written on the liquid crystal capacitor of the first subpixel SP-1, if the CS voltage supplied through the CS bus line CS-A after TFT-1 has been turned OFF increases, then the voltage at the liquid crystal capacitor of the first subpixel SP-1 is subjected to a voltage pull-up and rises. Consequently, the first subpixel SP-1 becomes a bright subpixel, of which the luminance is higher than the one associated with the source signal voltage supplied. On the other hand, if the CS voltage supplied through the CS bus line CS-B after TFT-2 has been turned OFF decreases, then the voltage at the liquid crystal capacitor of the second subpixel SP-2 is subjected to a voltage pull-down and falls. Consequently, the second subpixel SP-1 becomes a dark subpixel, of which the luminance is lower than the one associated with the source signal voltage supplied. In this manner, by displaying the luminance associated with the voltage supplied as the average of two mutually different luminances (i.e., an area average), or by superposing mutually different voltage-luminance characteristics (which will be sometimes referred to herein as “V-T characteristics”) of two subpixels one upon the other, the viewing angle dependence of the γ characteristic can be reduced.
In a liquid crystal display device with such a multi-pixel structure, a voltage, of which the waveform has a period that oscillates in a constant cycle time (and which will be simply referred to herein as an “oscillating voltage”) is used as the CS voltage. In that case, the bigger the size of a liquid crystal display device, the greater the load capacitance and resistance on a CS bus line. If one CS voltage cycle time is relatively short (e.g., equal to or shorter than one horizontal scanning period), then the waveform of the CS voltage will get blunted to a different degree according to the location within the display area. As a result, the display luminance will depend on the location within the display area, thus possibly making the luminances uneven. Patent Document No. 3 discloses a technique for minimizing or eliminating the occurrence of such luminance unevenness by extending one oscillation period of the CS voltage. The entire disclosures of Patent Documents Nos. 1 to 3 are hereby incorporated by reference.
If the voltages supplied to respective CS bus lines are controlled independently of each other, then the circuit configuration will get complicated but the waveforms of those CS voltages can be determined much more flexibly. That is to say, in that case, the CS voltages do not have to be oscillating voltages but may be determined so as to obtain desired effective values.
Meanwhile, a source line inversion drive method is known as a technique for cutting down the power dissipation of a driver for a liquid crystal display device (see Patent Document No. 4, for example). According to the source line inversion drive method, a source signal voltage of the same polarity is written on the same column of pixels (i.e., pixels that are connected to the same source bus line) among a plurality of pixels arranged in a matrix pattern as shown in FIG. 42. Meanwhile, to achieve uniformity on the display screen, voltages of mutually opposite polarities are supposed to be written on each pair of pixels that are adjacent to each other in the row direction. With this source line inversion drive method, the polarity of the source signal voltage needs to be inverted a much smaller number of times than a so-called “dot inversion drive method” in which source signal voltages of mutually opposite polarities are supposed to be written on every pair of pixels that are adjacent to each other in a column or row direction. As a result, the power dissipation can be cut down.
Furthermore, Patent Document No. 5 discloses a drive method in which scan lines (corresponding to gate bus lines and rows of pixels) are classified into multiple blocks, interlaced scanning is performed within each of those blocks but sequential scanning is performed between blocks, thereby supplying a data signal, which has had its order rearranged in line with the order of scanning of a scan signal, to a signal line driver (which will be referred to herein as a “block inversion drive method”). If such a block inversion drive method is adopted, the power dissipation can be reduced by lowering the polarity inversion drive frequency of the source signal voltage. On top of that, a flicker, crosstalk, vertical luminance gradient (in the column direction), interference to be caused due to interlaced scanning while a moving picture is presented (as horizontal comb contour) and other inconveniences can be eliminated. Nevertheless, if the block inversion drive is performed, the luminance may still get uneven between rows of pixels that are adjacent to each other in the column direction (i.e., along source bus lines) as will be described in detail later.                Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 11-242225        Patent Document No. 2: Japanese Patent Application Laid-Open Publication No. 2004-62146        Patent Document No. 3: Japanese Patent Application Laid-Open Publication No. 2005-189804        Patent Document No. 4: Japanese Patent Application Laid-Open Publication No. 8-202317        Patent Document No. 5: Japanese Patent Application Laid-Open Publication No. 11-352938        